Minimization of Permuted Reed-Muller Trees for Cellular Logic

The new family of Field Programmable Gate Arrays CLI from Concurrent Logic Inc realizes the truly Cellular Logic It has been mainly designed for the realization of data path architectures However introduced by it new universal logic cell calls also for new logic synthesis methods based on regularity of connections In this paper we present two programs exact and approximate for the minimization of Permuted Reed Muller Trees that are obtained by repetitive application of Davio expansions Shannon expansions for EXOR gates in all possible orders of variables in subtrees Such trees are particularly well matched to both the realization of logic cell and connection structure of the CLI device It is shown on several standard benchmarks that the heuristic algorithm gives good quality results in much less time than the exact algorithm